Generally, dynamic random access memories (DRAMS) are organized in a structure of two-dimensional cells in rows and columns. Memory cells may be accessed via wordlines, which are driven from row paths. Each cross point realizes an access to cell information of each cell connected to a selected wordline.
To achieve a high yield efficiency in semiconductor memories, redundancy array architecture is employed. Redundancy arrays are described by: Kalter et al., in "A 50-ns 16 MB DRAM with a 10-ns Rate and On-Chip ECC", IEEE Solid-State Circuits, Vol. 25, No. 5, Oct. 1990; and T. Kirihata, in "Fault-Tolerant Designs for 256 Mb DRAM", IEEE Solid-State Circuits, Vol. 31, No. 4, Apr. 1996, pp. 558-566. To distinguish non-redundancy memory arrays, cells, and wordlines from redundancy memory arrays, cells, and wordlines, the former group are hereinafter referred to as normal memory arrays, cells, and wordlines.
Redundancy array architecture allows a defective normal wordline WL.sub.i in any normal array to be replaced with a redundancy wordline RWL.sub.k in the redundancy array. In this scheme flexibility is high, and the number of reparable normal wordlines is increased. FIG. 1 is a diagram illustrating a common structure of a DRAM that includes a plurality of normal memory arrays 110 and a redundancy memory array 112, according to the prior art. A random access mode and a Cas-Before-Ras (CBR) mode of the DRAM arrays are depicted on the left and right sides of FIG. 1, respectively.
The random access mode allows data to be read from, or written to, DRAM cells coupling the corresponding normal wordline WL.sub.i in the activated normal memory array 110i (in a normal random access mode). If the normal wordline WL.sub.i is defective, it is replaced with the redundancy wordline RWL.sub.k in the redundancy memory array 112, allowing data to be read from, or written to, the DRAM cells coupling to the redundancy wordline RWL.sub.k (in a redundancy random access mode).
Due to the volatile nature of data storage in a DRAM cell, the DRAM includes a refresh operation that recharges the data of the DRAM cells. This refresh operation is generally enabled by a Cas-Before-Ras (CBR) command, and is called in a CBR mode. The CBR mode allows data to be refreshed for the DRAM cells coupling the corresponding normal wordline WL.sub.i in the activated normal memory array 110i (in a normal CBR mode). If the normal wordline WL.sub.i is defective, it is replaced with the redundancy wordline RWL.sub.k in the redundancy memory array 112 (in a redundancy CBR mode).
As the DRAM density increases, a CBR mode should activate more memory arrays (e.g., 110i and 110j) simultaneously than those activated in a random access mode. This is because activating more arrays refreshes more cells simultaneously in the CBR mode, thereby improving the random access mode utilization. Such a refreshing technique is commonly used for 64 Mb and larger DRAMs.
When a CBR mode needs to activate more than one memory array in the DRAM, there is a possibility of having more than one normal wordline WL.sub.i and WL.sub.j simultaneously replaced with the corresponding redundancy wordlines RWL.sub.k and RWL.sub.l, respectively. In this case, the chip becomes irreparable, because the bit data accessed by the redundancy wordlines RWL.sub.k and RWL.sub.l are conflicted on the bit-lines of the redundancy memory array 112. That is, since the pair of normal wordlines WL.sub.i and WL.sub.j are typically addressed together at the same time, they cannot be replaced with redundant wordlines in the redundancy memory array 112. This is because the row address signal addressing the pair of wordlines at the same time can address only one redundant wordline at a time in the redundancy memory array 112. While the use of two redundancy arrays would overcome the preceding problem, such use requires additional area to support the two redundancy arrays. Further, as the DRAM density increases, more wordlines may be activated simultaneously in a CBR mode. This increases the probability of the redundancy array contention.
Accordingly, based on the above description of the prior art, it would be desirable and highly advantageous to have a method that solves the problem of redundancy access contention in a CBR mode, without increasing the DRAM chip size.